The present invention relates to a storage device used as an external storage device for a computer or the like as well as to a control unit and a control method for the same.
As an external storage device for a computer or the like, there has been used a storage device having a magnetic disk as a storage medium. A memory capacity of a storage device is increasing in association with the increase in the performance of a main system of a computer and increase in a program size of software used in computers. Accordingly, also a recording density has been becoming substantially higher, and at the same time there is the strong need for size reduction.
FIG. 8 is a block diagram showing electrical configuration of a storage device 100 based on the conventional technology. In this figure, the storage device 100 comprises a HDA (head disk assembly) 110 having a shielding vessel consisting of a base and a cover for shielding the magnetic disks 1111 to 111n and magnetic heads 1131 to 113n packaged therein, a printed circuit board 120 with various types of circuits such as a HDC (hard disk controller) circuit 121A or a control circuit 125A printed thereon, and a connector 140 for electrically connecting the components of the HDA 110 to the printed circuit board 120. The storage device 100 is also connected to a CPU 150 provided in a main system of a computer not shown in the figure, and executes data write/read according to an instruction from the CPU 150.
In the HDA 110, magnetic disks 1111 to 111n are n sheets of storage medium each magnetically storing data therein, and are respectively provided in a layered form along the axis of rotation. An SPM (spindle motor) 112 rotates the magnetic disks 1111 to 111n at a high speed. Each of magnetic head 1131 to 113n comprises a cut ring shaped head core having an extremely narrow gap between the two ends and a coil wound around the head core, and the magnetic head 1131 to 113n are provided adjacent to the magnetic disks 1111 to 111n respectively.
The magnetic heads 1131 to 113n write a data into the magnetic disk 1111 to 111n according to a magnetic field generated by a recording current supplied to the coil when data is written therein, and they also detect the data stored in the magnetic disks 1111 to 111n as a regenerated voltage. The number of these magnetic heads are appropriately selected according to the number of the magnetic disks.
A carriage 114 is provided adjacent to the magnetic disks 1111 to 111n, and supports the magnetic heads 1131 to 113n. A VCM (voice coil motor) 115 moves the magnetic heads 1131 to 113n by rotating the carriage. An FPC (flexible print circuit sheet) 116 is a flexible wiring material having a form like a sheet and is used for connection between the carriage 114 and each terminal (not shown herein) of the connector 140.
Head IC (integrated circuit) 1171 and head IC 1172 each comprise a write amplifier and a preamplifier (both not shown herein), and are packaged on a surface of an FPC 116 in parallel to each other. The write amplifier switches the polarity of the recording current to be supplied to each of the magnetic heads 1131 to 113n according to write data supplied from the CPU 150, and the preamplifier amplifiers a regenerated voltage (read voltage) detected by each of the magnetic head 1131 to 113n.
Herein, a number of magnetic heads which can be controlled by one head IC (for instance, head IC 1171) is naturally limited, and when the number n of the magnetic heads 1131 to 113n exceeds the upper limit, two head ICs (in a case shown in the figure, the head ICs 1171 and 1172) are provided, and the magnetic heads 1131 to 113n are controlled by these two heads.
Thus, the head IC 1171 shown in this figure is provided for a specified number of magnetic heads of the magnetic heads 1131 to 113n, and the head IC 1172 is provided for the remaining ones of the magnetic heads 1131 to 113n.
When the number of magnetic heads 1131 to 113n does not exceeds the upper limit, the head IC 1172 need not be provided, and the magnetic heads 1131 to 113n may be controlled by only the head IC 1171.
Further the head IC 1171 and head IC 1172 output a first IC current I1 and a second IC current I2 from each terminal not shown herein when a select signal Ss described later is inputted and selected. The first IC current I1 and second IC current I2 are outputted via the FPC 116 to the connector 140.
The printed circuit board 120 is a board detachably attached via the connector 140 to a rear surface of the HDA 110, and the connector 140 plays as an interface between components of the HDA 110 and various circuits packaged on the printed circuit board 120. In the printed circuit board 120 described above, the HDC circuit 121A is connected via a SCSI (Small Computer System Interface) bus not shown herein to the CPU 150, and transacts various types of instruction, write data to be written in the magnetic disks 1111 to 111n and read data read out from the magnetic disks 1111 to 111n to the CPU 150 via the SCSI bus.
The HDC circuit 121A generates a select command Cs for selecting one of the head ICs 1171 and 1172, a control signal for controlling a format of recording and regeneration in the magnetic disks 1111 to 111n or the like. Detailed description of operations of the HDC circuit 121A is made later.
A buffer circuit 122 is a DRAM (Dynamic Random Access Memory) having a storage capacity of 512 K bytes, and temporally stores therein write data inputted from the CPU 150 and read data read out from the magnetic disks 1111 to 111n.
A ROM (Read Only Memory) 123 stores a program for write/read control executed by the HDC circuit 121A, and is accessed by the HDC circuit 121A when the program is to be executed. A RAM (Random Access Memory) 124 temporarily stores the data generated when the above program is executed.
A read/write circuit 129 has circuits such as a modulating circuit for writing write data in the magnetic disks 1111 to 111n, a parallel/serial converting circuit for converting parallel write data to serial data, a demodulating circuit for reading read data from the magnetic disks 1111 to 111n or the like.
Further, the read/write circuit 129 has circuits such as a serial/parallel converting circuit for converting serial read data to parallel data, a synthesizer circuit for generated a timing signal for controlling timing for each section of the device by multiplying a frequency of an oscillation circuit using a quartz oscillator or the like. When a select command Cs is inputted from the HDC circuit 121A, the control circuit 125A outputs a select signal Ss to any of the head IC 1171 and head IC 1172 via the connector 140 and FPC 116. Detailed description of operations of the control circuit 125A is made later.
A servo demodulating circuit 126 demodulates servo patterns for positioning stored in the magnetic disks 1111 to 111n by means of peak holding or integration. A VCM (Voice Coil Motor) driving circuit 127 drives the VCM 115, and has a power amplifier (not shown) for supplying a driving current to the VCM 115. A SPM (spindle motor) driving circuit 128 drives the SPM 112, and has a power amplifier (not shown) for supplying a driving circuit via the connector 140.
The control circuit 125A recognizes a servo pattern demodulated by the servo demodulating circuit 126, and controls a driving current supplied to the VCM driving circuit 127 and the SPM driving circuit 128 for providing positional controls over the magnetic heads 1131 to 113n. The control circuit 125A also controls the HDC circuit 121A, read/write circuit 129, buffer circuit 122.
A pull-up circuit 131 is packaged on the printed circuit board 120 and is electrically connected via the connector 140 to the FPC 116. Herein when two head ICs 1171 and 1172 are electrically packaged in the FPC 116, the pull-up circuit 131 is connected to the ground in the side of FPC 116. In this case, the pull-up circuit 131 outputs a pull-up voltage Vp (low-level voltage) when a power is supplied. Namely, when a pull-up voltage Vp from the pull-up circuit 131 is 0 V, it indicates that a number Nic of head ICs electrically connected to the FPC 116 (of head IC 1171 and head IC 1172 in the figure) is two.
On the other hand, when it is determined that only one head IC 1171 is electrically connected to the FPC 116, it indicates that the pull-up circuit is not connected to ground. In this case, the pull-up circuit 131 outputs a pull-up voltage Vp of 5 V (high-level voltage). Namely, when a pull-up voltage Vp from the pull-up circuit 131 is 5 V, it indicates that the number Nic of head ICs (head IC 1171 in the figure) electrically connected to the FPC 116 is one.
The current/voltage converting circuit 132 converts a synthesized current I0 (=first IC current I1+second IC current I2) inputted via the connector 140 to a IC voltage Vic. Herein, when two head ICs 1171 and 1172 are selected, as the first IC current I1 and second IC current I2 are outputted from the terminals respectively, so that the synthesized current I0 is a sum of the first IC current I1 and second IC current 12.
On the other hand, when only one head IC 1171 is selected, the first IC current I1 is outputted from a terminal of the head IC 1171, and the second IC current I2 is not outputted from the head IC 1172, so that the synthesized current I0 is equal to the first IC current I1.
As an example of the IC voltage Vic, when the number Nic of head ICs is two, namely when the synthesized current I0=(first IC current I1)+(second IC current I2), the IC voltage Vic is 1.0 V. On the other hand, when the number Nic of head ICs is one, namely when the synthesized current I0=first IC current I1, the IC voltage Vic is 3.0 V.
A reference voltage generating circuit 133A generates a reference voltage Vr (=1.7 V) used for comparison with the IC voltage Vic in a voltage comparing circuit 134. The voltage comparing circuit 134 compares the IC voltage Vic inputted from the current/voltage converting circuit 132 to the reference voltage Vr. When the IC voltage Vic is higher than the reference voltage Vr the voltage comparing circuit 134 outputs a comparison result voltage Vc of 5 V indicating a result of comparison to the control circuit 125A. The fact that the comparison result voltage Vc is 5 V indicates that only one head IC (for instance, head IC 1171) has been selected.
On the other hand, the voltage comparing circuit 134 outputs a comparison result voltage Vc of 0 V indicating a result of comparison to the control circuit 125A when the IC voltage Vic is lower than the reference voltage Vr. Herein, the fact that the comparison result voltage Vc is 0 V indicates that two head ICs (head ICs 1171 and 1172) are selected.
Operations of the storage device 100 based on the conventional technology will be described with reference to FIG. FIG. 9 and FIG. 10. FIG. 9 is a flow chart showing operations of the storage device 100 based on the conventional technology for recognizing (confirming) the number of ICs, while FIG. 10 is a flow chart showing a read/write processing in the storage device 100 based on the conventional technology.
Herein the operation for checking the number of ICs in FIG. 9 means an operation for making the HDC circuit 121A recognize the number Nic of head ICs electrically connected to the FPC 116 as an initial operation after a power is supplied to each section of the storage device 100. Herein, the reason for making the HDC circuit 121A recognize the number Nic of head ICs is that a method for the read/write processing changes according to the number Nic of head ICs.
On the other hand, the read/write control processing in FIG. 10 indicates a write operation for writing write data supplied from the CPU 150 in the magnetic disks 1111 to 111n and a read operation for reading read data from the magnetic disks 1111 to 111n.
In FIG. 8, it is assumed that two head ICs 1171 and 1172 are electrically connected to the FPC 116 and also that the pull-up 131 is grounded in the FPC 116 side. In this case, when a power is supplied to each section of the device, the HDC circuit 121A shifts the processing to step SA1 shown in FIG. 9, determines as to whether a pull-up voltage Vp has been inputted from the pull-up circuit 131 to the control circuit 125A or not. When it is determined that the pull-up voltage Vp has not been inputted from the pull-up circuit 131 to the control circuit 125A the same operation is repeated.
When a power is supplied to the pull-up circuit 131, as the pull-up circuit 131 is connected to ground it outputs a pull-up voltage Vp of 0 V (low-level voltage) to the control circuit 125A. The HDC circuit 121A determines that the result of determination in step SA1 as xe2x80x9cYesxe2x80x9d and shifts the processing to step SA2. In step SA2, the HDC circuit 121A determines whether the pull-up voltage Vp inputted into the control circuit 125A is 5 V(high-level voltage) or not. In this case, the HDC circuit 121A recognizes the result of determination as xe2x80x9cNoxe2x80x9d and then shifts the processing to step SA5. In step SA5, the HDC circuit 121A recognizes according to the pull-up voltage Vp (=0 V) that the number Nic of ICs is two, shifts the processing to step SA4 and then executes the read/write control processing.
On the other hand, when only one head IC 1171 is connected and at the same time the pull-up circuit 131 is not connected to the ground, as a pull-up voltage Vp outputted from the pull-up circuit 131 to the control circuit 125A is 5 V (high-level voltage) the HDC circuit 121A recognizes that a result of comparison in step SA2 is xe2x80x9cYesxe2x80x9d and shifts the processing to step SA3. In step SA3, the HDC circuit 121A recognizes according to the pull-up voltage Vp (=5 V) that the number Nic of ICs is one, shifts the processing to step SA4 and then executes the read/write control processing.
Description is made for the read/write control processing when the number Nic of ICs is two, namely when the HDC circuit 121A shifts the processing from step SA5 to step SA4 in FIG. 9 with reference to FIG. 10.
Assuming that a command for writing write data in the magnetic disks 1111 to 111n, or a command for reading read data from the magnetic disks 1111 to 111n is inputted from the CPU 150 shown in FIG. 8 to the HDC circuit 121A, the HDC 121A shifts the processing to step SB1 shown in FIG. 10. In step SB1, the HDC circuit 121A selects a head IC to be used for read/write from or to the magnetic disks 1111 to 111n out of the two head ICs 1171 and 1172 recognized in step SA5 (Refer to FIG. 9). In this case, if the head IC 1171 is selected, the HDC circuit 121A outputs a select command Cs indicating a result of the selection above to the control circuit 125A.
In step SB2, the control circuit 125A outputs a select signal Ss via the connector 140 and FPC 116 to the head IC 1171. In step SB3, the current/voltage converting circuit 132 determines whether the synthesized current I0 is inputted or not and waits till the synthesized current I0 is inputted.
When the select signal Ss is inputted into the head IC 1171, the first IC current I1 is outputted as the synthesized current I0 from a terminal of the head IC 1171 via the FPC 116 and connector 140 to the current/voltage converting circuit 132. The current/voltage converting circuit 132 shifts the processing from step SB3 to step SB4, converts the inputted synthesized current I0 to the IC voltage Vic (=3.0 V), and then outputs the IC voltage Vic to the voltage comparing circuit 134.
In step SB5, the voltage comparing circuit 134 compares the inputted IC voltage Vic (=3.0 V) with the reference voltage Vr (1.7 V) inputted from the reference voltage generating circuit 133A and then shifts the processing to step SB6. In step SB6, the voltage comparing circuit 134 determines whether the IC voltage Vic is higher than the reference voltage Vr or not, and as the IC voltage Vic is higher than the reference voltage Vr in this case, recognizes that a result of determination in step SB6 is xe2x80x9cYesxe2x80x9d and then shifts the processing to step SB7.
In step SB7, the voltage comparing circuit 134 outputs the comparison result voltage of 5 V (high-level voltage) indicating a result of comparison to the control circuit 125A. With this operation, in step SB8, the HDC circuit 121A recognizes that a head IC has been selected normally, and shifts the processing to step SB9. Herein normal selection indicates that the select signal Ss is inputted only to the head IC 1171 selected in step SB1, and that the selected head IC 1171 is operating normally. In step SB9, the HDC circuit 121A executes read/write controls over the magnetic disks 1111 to 111n by controlling each section of the device according to a command from the CPU 150.
On the other hand, in step SB2, it is assumed that the select signal Ss was outputted to both the head ICs 1171 and 1172 due to a trouble or for some other reasons in spite that it was instructed to output the select signal Ss via the connector 140 and FPC 116 from the control circuit 125A only to the head IC 1171. Namely, in this case, in spite that the HDC circuit 121A selected one head IC 1171, two head ICs 1171 and 1172 were selected due to a trouble or for some other reasons.
Then, when the select signal Ss is inputted into both the head ICs 1171 and 1172, a sum of the first IC current I1 and second IC current I2 is outputted as the synthesized current I0 from terminal of the head ICs 1171 and 1172 via the FPC 116 and connector 140 to the current/voltage converting circuit 132. Therefore, the current/voltage converting circuit 132 shifts the processing from step SB3 to step SB4, converts the inputted synthesized current I0 to the IC voltage Vic (=1.0 V), and outputs the IC voltage Vic to the voltage comparing circuit 134. In step SB5, the voltage comparing circuit 134 compares the inputted IC voltage Vic (=1.0 V) with the reference voltage Vr (1.7 V) inputted from the reference voltage generating circuit 133A, and then shifts the processing to step SB6. In step SB6, as the IC voltage Vic is lower than the reference voltage Vr, the voltage comparing circuit 134 recognizes a result of determination in step SB6 as xe2x80x9cNoxe2x80x9d, and shifts the processing to step SB10.
In step SB10, the voltage comparing circuit 134 outputs a comparison result voltage Vc of 0 V indicating a result of comparison to the control circuit 125A. In step SB10, the HDC circuit 121A recognizes that two head IC have been selected, namely that an abnormal state (trouble) has been generated, shifts the processing to step SB12 and terminates the read/write control processing.
In the above description, it is assumed that the number Nic of head ICs electrically connected to the FPC 116 in the storage device 100 is two, but hereafter description is made for an another storage device in which the number Nic is three with reference to FIG. 11.
FIG. 11 is a block diagram showing electrical configuration of a storage device 200 having the conventional type of configuration. In this figure, the same reference numerals are assigned to the same components as those in FIG. 8 and description thereof is omitted herein. In FIG. 11, a HDC circuit 121B and a control circuit 125B are provided in place of the HDC circuit 121A and control circuit 125A shown in FIG. 8, and a head IC 1173 and a pull-down circuit 135 are added. In FIG. 11, a read/write circuit 129 also provides read/write controls over the third head IC 1173.
The head IC 1173 shown in FIG. 11 has the same functions as those of the head ICs 1171 and 1172, and is provided in parallel with the head ICs 1171 and 1172 on a surface of the FPC 116. The basic functions of the HDC circuit 121B are the same as those of the HDC circuit 121A, however it outputs a select command Cs for selecting one of the three head ICs 1171 to 1173 to the control circuit 125B, and provides read/write controls using these three head ICs 1171 to 1173. It should be noted that detailed description is made later for operations of the HDC circuit 121B and control circuit 125B.
The pull-down circuit 135 is packaged on the printed circuit board 120, and is electrically connected via the connector 140 to the FPC 116. Also the pull-down circuit 135 is grounded in the side of FPC 116. In this state of connection, when a power is supplied, the pull-down circuit 135 outputs a pull-down voltage Vd of 0 V (low-level voltage) to the control circuit 125B.
On the other hand, the pull-up circuit 131 packaged in parallel with the pull-down circuit 135 is not connected to the ground in the FPC 116 side. Therefore, when a power is supplied, the pull-up circuit 131 outputs a pull-up voltage Vp of 5 V (high-level voltage) to the control circuit 125B. Namely, when a pull-down voltage Vd from the pull-down circuit 135 is 0 V (low-level voltage) and at the same time a pull-up voltage Vp from the pull-up circuit 131 is 5 V (high-level voltage), it indicated that the number Nic of head ICs electrically connected to the FPC 116 (head ICs 1171 to 1172 in the figure) is three.
Description is made for operations of the conventional type of storage device 200 for checking the number of ICs with reference to FIG. 12. Herein the operation for recognizing the number of ICs means an operation for making the HDC circuit 121B recognize the number Nic of head ICs electrically connected to the FPC 116 as an initial operation after a power is supplied to each section of the storage device 200.
In FIG. 11, when a power is supplied to each section of the device, the HDC circuit 121B shifts the processing to step SC1 shown in FIG. 12 with a pull-up voltage Vp (=5 V) inputted from the pull-up circuit 131 to the control circuit 125B, and determines whether a pull-up voltage (=0 V) has been inputted from the pull-up circuit 135 or not, and, when a result of determination is xe2x80x9cNoxe2x80x9d, repeats the determination.
When a power is supplied to each of the pull-up circuit 131 and pull-down circuit 135, the pull-up circuit 131 outputs a pull-up voltage Vp (=5 V) to the control circuit 125B, and the pull-down circuit 135 outputs a pull-down voltage Vd (=0 V) to the control circuit 125B. The HDC circuit 121B recognizes that a result of determination in step SC1 is xe2x80x9cYesxe2x80x9d and shifts the processing to step SC2. In step SC2, the HDC circuit 121B recognizes that the number Nic of ICs is three, shifts the processing to step SC3, provides the read/write controls as shown in FIG. 10, and executes the read/write control processing using the three head ICs 1171 to 1173.
In the conventional types of storage devices as described above, there are strong needs for simplifying the configuration, reducing the size and the cost by reducing an area required for packaging or required components in association with the tendency for higher performance and size reduction of computers. At the same time, there are also the needs for larger storage capacity and higher recording density, which necessitates packaging of components each with complicated circuit configuration on a printed circuit board having a limited packaging area.
In the conventional type of storage device 100 as shown in FIG. 8, as the pull-up circuit 131 used only for recognizing the number of ICs is packaged on the printed circuit board 120, an additional area for packaging must be acquired on the printed circuit board 120, and this need has not fully been satisfied in the conventional technology.
Especially, when the number Nic of head ICs is three like in a case of the storage device 200 shown in FIG. 11, in addition to the pull-up circuit 131, also the pull-down circuit 135 is required to additionally be packaged on the printed circuit board 120, which makes it difficult to achieve the above-described objects of simplification, size reduction, and cost reduction.
It is an object of the present invention to provide a storage device which allows simplification of configuration, size reduction, and cost reduction as well as a control unit and a control method for the same.
With the present invention, all of the head ICs are selected by a selecting unit, and if the number of head ICs is one, an IC current is inputted as a synthesized current from this head IC to an IC number checking unit. From the inputted synthesized current the IC number checking unit recognizes that the number of head ICs is one. On the other hand, when the number of head ICs is plural and all of the head ICs are selected by the selecting unit, IC currents are outputted from each of the head IC, and the IC currents are summed up into a synthesized current that is inputted into the IC number checking unit. From the inputted synthesized current the IC number checking unit recognizes that the number of head ICs is plural.
According to the present invention, the number of head ICs is confirmed according to the synthesized current obtained by synthesizing the IC currents, so that a circuit dedicated for confirming the number of ICs as required in the conventional technology is not necessary, and a packaging area equivalent to the packaging area of such a dedicated circuit can be reduced.
With the present invention, when all of the head ICs are selected by a selecting unit, IC currents from each of the head ICs are summed up to get a synthesized current that is inputted into a current/voltage converting unit. The current/voltage converting unit converts the synthesized current to an IC voltage, and a comparing unit compares the IC voltage to a reference voltage. An IC number confirming unit confirms from a result of comparison by the comparing unit whether the number of head ICs is one or plural.
According to the present invention, whether the number of head ICs is one or plural is confirmed according to a result of comparison by the comparing unit, so that a circuit dedicated for confirming the number of ICs as required in the conventional technology is not necessary, and a packaging area equivalent to the packaging area of such a dedicated circuit can be reduced.
With the present invention, all of the head ICs are selected by a selecting unit, and when the number of head ICs is one, an IC current from this head IC is inputted as a synthesized current into an IC number confirming unit. From the inputted synthesized current the number checking unit recognizes that the number of head ICs is one. On the other hand, when there are a plurality of head ICs and all of the head ICs are selected by the selecting unit, IC currents are outputted from each of the head ICs and the IC currents are summed up to get a synthesized current that is inputted into the IC number checking unit. From the inputted synthesized current the IC number confirming unit recognizes that the number of head ICs is plural.
According to the present invention, the number of head ICs is confirmed according to a synthesized current obtained by synthesizing IC currents, so that a circuit dedicated for confirming the number of ICs as required in the conventional technology is not necessary, and a packaging area equivalent to the packaging area of such a dedicated circuit can be reduced.
With the present invention, when all of the head ICs are selected by a selecting unit, IC currents are outputted from each of the head ICs and are summed up to get a synthesized current that is inputted into a current/voltage converting circuit. The current/voltage converting unit converts the synthesized current to an IC voltage, and a comparing unit compares the IC voltage with a reference voltage. An IC number confirming unit confirms according to a result of comparison by the comparing unit whether the number of head ICs is one or plural.
According to the present invention, whether the number of head ICs is one or plural is checked according to a result of comparison by the comparing unit, so that a circuit dedicated for confirming the number of ICs as required in the conventional technology is not necessary, and a packaging area equivalent to the packaging area of such a dedicated circuit can be reduced.
With the present invention, all of the head ICs are selected in a selecting step, and when the number of head ICs is one, an IC current is outputted as a synthesized current from this head IC. In an IC number confirming step it is recognized according to the synthesized current that the number of head ICs is one. On the other hand, when there are a plurality of head ICs all of the head ICs are selected in the selecting step and the IC currents outputted from each of the head ICs are summed and outputted as a synthesized current. Thus, in the IC number confirming step it is recognized according to the synthesized current that the number of head ICs is plural.
According to the present invention, the number of head ICs is confirmed according to the synthesized current obtained by synthesizing the IC currents, so that a circuit dedicated for confirming the number of ICs as required in the conventional technology is not necessary, and a packaging area equivalent to the packaging area of such a dedicated circuit can be reduced.
With the present invention, head ICs are selected in a selecting step, and IC currents are outputted as a synthesized current from the head ICs. The synthesized current is converted to an IC voltage in a current/voltage converting step, and the IC voltage is compared with a reference voltage in a comparing step. In an IC number confirming step, whether the number of head ICs is one or plural is confirmed according to a result of comparison in the comparing step.
According to the present invention, whether the number of head ICs is one or plural is confirmed according to a result of comparison in the comparing step, so that a circuit dedicated for confirming the number of ICs as required in the conventional technology is not necessary, and a packaging area equivalent to the packaging area of such a dedicated circuit can be reduced.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.